This invention pertains to fabricating a semiconductor surface with one or more protrusions, such as pillars or walls. The invention is described in the context of its use as a surface shaping template/support structure for another surface, such as a capacitor plate.
FIG. 1 shows a conventional volatile memory cell 10 such as is used in a DRAM or SDRAM. Advantageously, a two-dimensional array of such cells 10 are provided which are organized into rows and columns. Each row of cells is provided with a word line and each column of cells is provided with one or more bit lines. Each cell is connected to the word line of the row, and at least one of the bit line(s) of the column, into which the cell 10 is organized. A particular cell is accessed (i.e., a bit is written thereto or read therefrom) by activating (i.e., applying a voltage to, or sensing a voltage on,) the word line and bit line(s) connected to the to-be-accessed cell. As shown in FIG. 1, the cell 10 illustratively comprises a switch, in the form of a MOSFET transistor 12. The gate of the MOSFET 12 is connected to the word line WL of the row containing the cell. The drain of the MOSFET 12 is connected to the bit line BL of the column containing the cell. Connected to the source of the MOSFET is a capacitor 14. By activating the word line WL and the bit line BL, a charge can be stored on, or removed from, the capacitor 14, or the particular charge of the capacitor 14 can be sensed.
It is desirable to increase the amount of charge that can be stored on the capacitor 14 of each cell. By increasing the charge stored on the capacitor 14, the correct logic value stored in the cell 10 can be more easily sensed. As is known, the amount of charge Q stored on the capacitor 14 is a function of the capacitance C of the capacitor 14 and the voltage V applied to the cell 10 during the writing operation (i.e., Q=CV). Generally speaking, the applied voltage is fixed, e.g., at 5 volts, 3.3. volts, etc.
The capacitance C, on the other hand, is a function of, amongst other things, the surface area of the capacitor plates. That is, the capacitance of the capacitor increases with increasing surface area of the capacitor plates. However, as device dimensions of the memory, in particular, the cells 10, are reduced, or the number of cells in the array are increased, or both, less planar surface area of the semiconductor die is available for allocation to the capacitor plate of each cell. To overcome this problem, the prior art has suggested several techniques for changing the geometry of the capacitor plates from planar, two-dimensional structures to non-planar, three-dimensional structures. See, e.g., U.S. Pat. Nos. 5,512,768, 5,492,848, 5,482,885, 5,482,882, 5,466,627, 5,459,095, 5,427,974, 5,350,707, 5,332,696, 5,302,540, 5,256,587, 5,213,992, 5,168,881, and 5,158,905; Y. K. Jun, S. K. Rha, S. C. Kim, J. S. Roh, W. S. Kim & H. G. Lee, The Fabrication and Electrical Properties of Modulated Stacked Capacitor for Advanced DRAM Application, IEEE ELEC. DEV. LETTERS, vol. 13, no. 8, Aug., 1992, p. 430-432.
FIG. 2 shows an illustrative template/support structure 30 which, for example, can be used in forming a capacitor plate with increased surface area. As shown, multiple protrusions (e.g., walls or pillars) 32 are formed in a substrate. Each protrusion 32 includes a nitride region 34, such as Si.sub.3 N.sub.4, formed on a Si mesa 36. A low pressure (e.g., 40 torr) O.sub.3 /TEOS (ozone/tetraethylorthosilicate) film 38 is deposited on, and covers the top surface of, the nitride regions 34, the top surfaces of the substrate portions 37 separating the protrusions 32 and the side surfaces of the Si mesas 36 and nitride regions 34. A capacitor plate, e.g., of a doped polycrystalline Si, can then be formed on the O.sub.3 /TEOS film 38. The capacitor plate will have a three-dimensional surface that conforms to the surface of the top and side surfaces of the protrusions 32 of the template/support structure and separating substrate surface portions 37. Thus, for a given planar area of the semiconductor die, a capacitor plate can be formed with a larger surface area, and thus a larger capacitance C.
The use of the low pressure O.sub.3 /TEOS film 38 provides certain advantages such as relatively complete and uniform thickness coverage over the top and side surfaces of each protrusion 32 of the structure 30. However, the use of low pressure O.sub.3 /TEOS in the film 38 is also associated with certain disadvantages. For example, such a low pressure O.sub.3 /TEOS film 38 has a low water resistance. This means that the film 38 tends to absorb a large amount of water when exposed to air. This can change the geometry (size, shape) of the film 38 in an undesirable fashion. In addition, the low pressure O.sub.3 /TEOS film 38 has a high water content. Thus, if heated at a later time this water may boil out thereby damaging the structure 30 or other parts of the die. Furthermore, the low pressure O.sub.3 /TEOS film 38 is porous. At high temperatures, such as 1000.degree. C. or higher, the film can shrink 11% or more. Likewise, the porous nature of the low pressure O.sub.3 /TEOS film 38 makes it etch at an uncontrollably high rate. For example, more than 10,000 .ANG./min are etched away in a BOE 7:1 (a buffered oxide etch using an etching agent, such as a mixture of 49% HF with NH.sub.4 F, at a volume ratio of 1 to 7).
It is an object of the present invention to overcome the disadvantages of the prior art.